This invention relates generally to integrated circuit resistors, and more specifically to high value integrated circuit resistors formed from polycrystalline silicon.
High value integrated circuit resistors are often fabricated from lightly doped polycrystalline silicon. The same layer of polycrystalline silicon used to effect the resistor is also used as the gate electrode of MOS devices and/or as an interconnect to couple together the various devices used to achieve the desired integrated circuit function. The implementation of polycrystalline silicon resistors in the conventional manner, however, has required choosing between alternatives and making compromises either in the properties of certain circuit components or in the ease of manufacture of the circuit.
Although it is possible to achieve high sheet resistivity in polycrystalline silicon films of nominal thickness by lightly doping the polycrystalline silicon, for example by ion implantation, it difficult to control the sheet resistivity in the desired range because of the steep relationship between doping and resistivity. Small changes in impurity doping can make very large changes in sheet resistivity. Because of this, resistors have been implemented by using more heavily doped and thus more controllably doped polycrystalline silicon which has a lower sheet resistivity and then relying on geometric factors to achieve the high resistance. For example, high value resistors are fabricated from thin layers of polycrystalline silicon or are formed from thicker layers patterned to have a large length to width ratio either by making the resistor long or by making the resistor narrow. The use of thin polycrystalline silicon has a number of disadvantages, including, most notably, the problem that the thin and high resistance polycrystalline silicon is inappropriate for use as an interconnection. Additionally, thin polycrystalline silicon is difficult to contact because of factors relating to the alloying properties of aluminium and silicon. Long resistors require too much area on the integrated circuit chip being fabricated and narrow resistors are difficult to control because small dimensional changes can represent a large percentage change.
Some of these problems have been overcome in the past, for example, by thinning the polycrystalline silicon in the region where the resistor is fabricated and leaving the polycrystalline silicon at nominal thickness where it is used to implement interconnections and gate electrodes. This procedure is less than satisfactory because of the difficulty encountered in controllably thinning the polycrystalline silicon. Additionally, one layer of polycrystalline silicon can be used to implement the resistor and another or additional layer of polycrystalline silicon can be used to implement the interconnection and gate electrodes. This, however, requires, in addition to the deposition of an extra layer of polycrystalline silicon, the patterning of the additional layer and especially the alignment of the patterning of the first and second layers.
Accordingly, a need existed for an improved process for fabricating integrated circuit resistors which would provide high value resistors, would be manufacturable, and would be consistent with interconnecting the high value resistors with other circuit components.
It is therefore an object of this invention to provide an improved process for fabricating polycrystalline silicon integrated circuit resistors.
It is another object of this invention to provide an improved process for fabricating integrated circuit resistors interconnected with other circuit devices.